Role : Physical Design Engineer Location: Markham, Canada Job Description: • Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Synopsys/Cadence EDA tools (Preference: 5) Job Responsibility • Expertise in understanding constraints and fixing design/timing techniques • Expertise in timing closure (STA) of high frequency blocks • Experience performing detailed synthesis for blocks of high instance counts and complex designs – 1M+ instances and clock frequencies about 1 GHz • Knowledge of signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level • Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge. • Experience in Block-level and Full-chip integration. • Proficient in Synopsys Fusion Compiler, Design Compiler, Cadence Innovus, PTSi • Experience in Design Automation and UNIX system. • Experience in Tcl/Tk, PERL, Python is a plus. Desired Skills & Experience: • Must possess solid experience in handling block/chip level implementation from RTL to GDSII • Must possess hands on experience in timing closure of blocks and full-chip • Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz • Experience in handling lower tech nodes that include 3nm, 5nm, 7nm, 10nm, 16nm, etc. • Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such as Design Compiler, Fusion Compiler or Innovus. • Must have the ability to think on the spot for quick solutions and work-around at the time of tape-out to hit the schedule on time • Must possess excellent scripting skills – TCL or Perl or Python • Experience in Synthesis and Formal is a MUST • Excellent verbal and written communication skills are required. • Must possess excellent debug skills, analytical skills, and the ability to work independently. • Must be highly motivated and possess excellent team spirit