We are currently seeking a highly skilled Physical Design Engineer to support advanced SoC development efforts. This is an exciting opportunity to work with cutting-edge technologies in a high-performance design team. The ideal candidate will have hands-on experience in RTL-to-GDSII implementation, timing closure, and low-power design for high-frequency, large-scale digital circuits.
Responsibilities:
- Develop block and SoC-level timing constraints
- Perform full-chip static timing analysis (STA) setup and signoff
- Lead timing closure for high-frequency blocks (1GHz+) with 1M+ instance count
- Conduct synthesis for large and complex digital designs
- Drive signoff closure for timing (SI, OCV), IR drop, power, and physical verification
- Implement low-power design techniques including UPF, power gating, and multiple voltage rails
- Collaborate on block-level and full-chip integration
- Support design automation workflows and UNIX-based environments
- Create and maintain scripts in Tcl, PERL, or Python
Requirements:
- 5+ years of hands-on experience in physical design engineering
- Expertise in RTL-to-GDSII implementation and STA
- Experience with Synopsys Fusion Compiler, Design Compiler, Cadence Innovus
- Strong understanding of advanced technology nodes (3nm to 16nm)
- Tape-out experience at lower tech nodes
- Excellent debugging, scripting, and problem-solving skills
- Experience with formal verification and synthesis required
- Strong communication and teamwork skills
Nice to Have:
- Experience with PTSi and formal signoff tools
- Exposure to advanced chip architecture and active/active design setups.